In some conventional integrated circuits (ICs), the ICs are designed as a collection of functional blocks that are physically arranged on a die for fabrication. When an IC is complex and relatively large, blocks frequently end up being placed far enough apart that differences in the propagation delay of signals to the blocks, and between the blocks, may affect the behavior of the IC in undesirable ways.
In instances where the signal may be coupled to multiple blocks that are not placed in close physical proximity on the IC die, there may be significant differences in the propagation delay as signals propagate from a source to one or more destination blocks. In this regard, the signal's arrival time at each of the destination blocks may be different based on the physical arrangement of the blocks on the die. In operation, it may be critical that one of the blocks receives the input signal before another block, independent of the manner in which the blocks are physically arranged.
Furthermore, it may also be critical that one block does not receive the input signal unless another block also receives it. If the input signal takes completely different paths to each block, the paths may have different buffering logic that may react differently to signal glitches. Therefore, it may be possible for a glitch to reach one block and not the other. Depending on the system requirements, this may have catastrophic effects, such as, for example, invalid data being latched resulting in calculation of a completely useless output, or a state machine transitioning to a different state than it should and therefore being “out of sync” with other blocks and performing unexpected and undesired functions.
FIG. 1 is a block diagram of a conventional system that illustrates problems associated with signal propagation in an integrated circuit. Referring to FIG. 1, there is shown a general logic block (GLB) 102, a reset processing block (RPB) 104, and a special logic block (SLB) 106.
The GLB 102 may comprise decode testmode module (DTM) 110, general decode module (GDM) 112, a latch 114 and a buffer 116. The DTM 110 comprises suitable logic, circuitry and/or code that may be adapted to decode input signals such that the DTM 110 may generate a test mode signal that may indicate to the chip that a test of the chip may take place. The latch 114 may temporarily hold the signal generated by the DTM 110. The GDM 112 comprises suitable logic, circuitry and/or code that may be adapted to the chip to function in a normal mode. The RPB 104 may comprise input processing module (IPM) 120 and a buffer 122. The IPM 120 comprises suitable logic, circuitry and/or code to process an input reset signal for use inside the chip. The SLB 106 may comprise a buffer 130 and special logic module (SLM) 132. The SLM 132 comprises suitable logic, circuitry and/or code so that the SLM 132 may configure the chip for a chip test mode. The buffers 116, 122 and 130 may be used to add delay to a signal path, to buffer a signal to isolate a signal, and/or to increase the strength of the signal.
The RPB 104 may be adapted to receive and process an input reset signal 150. For example, RPB 104 may be adapted to synchronize the received input reset signal 150 to a system clock in order to generate the processed reset signal 152 for distribution to other blocks. The GLB 102, which may generally be the logic for the specific functionality of the chip in the normal operating mode, may receive a processed reset signal 152 from RPB 104 and may utilize the processed reset signal 152 to initialize or configure circuitry in the GLB 104 to a known state. The SLB 106 may be utilized for internally testing the chip, and may also receive the processed reset signal 152.
A chip design may include a signal that is used in multiple blocks. For example, in FIG. 1, the GLB 102 and the SLB 106 may utilize the processed reset signal 152. The processed reset signal 152 may be communicated to SLB 106 where it may be buffered by buffer 130 to generate a first reset signal 154 that may then be used to reset SLM 132. The processed reset signal 152 may also be communicated to the GLB 102 where it may be buffered by the buffer 116 to generate a second reset signal 156 that may be used to enable latch 114. The input to the latch 114 may be a signal indicating that the chip, comprising the GLB 102, the RPB 104, and the SLB 106, may be tested. An output signal testmode_enable 142 from the latch 114 may be a signal that may be utilized by the SLM 132 to select the chip for test mode. Therefore, there may be a requirement that the different blocks receive the first and second reset signals 154 and 156 in a specific order to function properly.
If, for example, the SLM 132 must be reset before the output of the latch 114 changes, the exemplary system of FIG. 1 may not function as desired. In this example, if a propagation delay for the processed reset signal 152 is longer from the RPB 104 to the SLB 106 than a propagation delay from the RPB 104 to the GLB 102, then the second reset signal 156 may enable the latch 114 before the first reset signal 154 may reset the SLM 132, and the output signal testmode_enable 142 from latch 114 may change before the SLM 132 may be reset. A result may be that the SLM 132 may not be reset before the rising edge of testmode_enable 142 which may cause improper operation. As another example, a glitch may occur on the reset signal 152. Due to differences in the characteristics of buffers 130 and 116, the latch 114 may see the reset, and the SLM 132 may not. This would result in the testmode_enable signal 142 being asserted without the SLM 132 getting reset at all.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.